Cost effective reconfigurable logic
To develop a methodology to replace the high cost FPGA chip by low cost microcontroller in order to support low speed applications by converting verilog HDL code to assembly code and redesigning the basic architecture of microcontroller.
| Startup type: | Competition Entry |
| Status: | Active |
| Stage: | Just An Idea |
| Publicity: | Open to speaking to journalists. |
| Funding: | Self-funded |
| Industries: | Nanotech |
| Location: | san jose , CA, USA |
| Website: | http://younoodle.com |
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Piyush Patel
B.E. in Electronics and Communication from North Gujarat University (2006), MS in General Engineering from San Jose State University (2010), Design Engineer for R & D at Amtech Electronics (2007), Lab Monitor at Department of Mathematics since 2009.