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Zhenyu Tang

Electrical Engineering graduate from Tsinghua University with MSc from Chinese Academy of Sciences and MSc in Computer Engineering from University of Wisconsin - Madison. Currently working as Technical Manager at Intel Corporation.

Headline:	Entrepreneur
Skills:	C/C++, Computer Engineering, Electrical Engineering, Engineering, Languages and Platforms, Perl, Software Engineering
Groups:	2011 UC Berkeley Business Plan Competition, 2012 UC Berkeley Startup Competition, UC Berkeley Business Plan Competition 2009-2010
Interested in:	Brainstorming, Finding business partners, Finding cofounders, Finding team mates, Meeting new people, Professional opportunities, Promoting my startups, Recruiting for my startup
Schools:	University of Wisconsin System - Madison

FULL BIO

• Eight years of experience in low-power high-performance VLSI circuit design
• Three years of management experience
• Technical leader, power owner and key circuit designer for the first 45nm microprocessor of Intel
• Two book chapters, several journal and conference papers published, one patent granted
• Marathon runner and Captain of Intel sand volleyball league champion

WORK EXPERIENCE

Employer:	Intel Corporation, Santa Clara, CA
Position:	Technical Manager, Leader and Staff Hardware Design Engineer
Time period:	April 2002 - Present
Description:	Technical manager and cluster level power owner for cache coherent unit design in the next generation Xeon microprocessor - Leading a design team with eight designers - Responsible for all datapath design in the cache coherent unit - Guiding power estimation, projection and reduction methodology - Hand on experience in latest Synopsys DCT and ICC synthesis design - Project Award winner by improving project productivity Cluster level power owner, technical leader and key circuit designer for the first 45nm microprocessor (Penryn) in the world, which is the latest generation of Centrino. - Technical leader for microprocessor BUS circuit design - Manager of layout designers - Project Award winner due to contribution on power reduction methodology - Key designer of low-power high-performance circuits including dynamic circuit, register file memory and tri-state bus. - Responsible for all back-end verification flows including critical timing paths and race paths fix, slope and pulse width check, power reduction, ERC, noise and SCH2RTL verification. Circuit designer for IA-64 Itanium server processor: Tukwila, Montecito, Dunnington - Designer of low-power high-performance circuit in IEU and on-die memory controller, including large register file, ECC XOR tree, syndrome decoder, etc. - Synthesis of control block of on-die memory controller - RTL design of control blocks of on-die memory controller

Employer:	Compaq Corporation, Palo Alto, CA
Position:	Hardware Design Engineer
Time period:	July 2001 - March 2002
Description:	Circuit designer for Compaq EV7 server processor

Employer:	HP Research Lab, Palo Alto, CA
Position:	Summer Internship
Time period:	May 2000 - August 2000
Description:	Micro-architecture level power estimation and reduction techniques for processor

Employer:	ECE Department, University of Wisconsin – Madison
Position:	Research Assistant
Time period:	January 2000 - May 2001
Description:	Projects including: Design and Implementation of Destination Reorder Buffer, Power Aware Synchronous RS232 Transmitter and Receiver Implementation, WISC-F00 Pipeline Processor, etc

Employer:	ECE Department, University of Wisconsin – Madison
Position:	Teaching Assistant
Time period:	January 2000 - May 2001
Description:	Directing FPGA based design projects including development of organization, architecture, logic, placement, routing, simulation and debugging.

EDUCATION

University:	University of Wisconsin System - Madison
Time period:	2001
Degree:	Computer Engineering, MSc

PUBLICATIONS

Papers:

- H. Li, Z. Tang, K. Sit, S. Jamshidi, chapter “Active Power Reduction”, textbook “Computer Engineering Handbook”, 2008
- Z. Tang, N. Chang, S. Lin, etc, “Ramping Functional Units for Inductive Noise Reduction,” Springer Lecture Notes in Computer Science -- Power Aware Computer Systems, edited by B. Falsafi and T. N. Vijaykumar, 2001.
- Z. Tang, N. Chang, S. Lin, W. Xie, S. Nakagawa, and L. He, "Instruction prediction for step power reduction," IEEE International Symposium on Quality of Electronic Design, March 2001.

Patents:

- Z. Tang, Y. Xu, P. Yao, Z. Wang, “High-Volume High-Speed Digital Signal System Built on PCI Bus”, Patent ZL01131693.4, China, June 2005