Suhanya Ramakrishnan
Electronics and Instrumentation Engineering graduate from University of Madras, MSc degree from University of Wisconsin. 5 years experience in microprocessor design and implementation over multiple projects and tape-outs, now at Micron Technology.
| Headline: | Engineer |
| Skills: | C/C++, Computer Engineering, Design, Electrical Engineering, Engineering, Languages and Platforms, Perl, Software Engineering, System Administration, Unix, Windows |
| Groups: | BASES |
| Interested in: | Consulting opportunities, Finding team mates, Meeting new people, Providing services to startups, Trading services |
| Schools: | University Of Madras, University of Wisconsin System - Madison |
WORK EXPERIENCE
| Employer: | Micron Technology |
| Position: | Sr. Design Engineer |
| Time period: | July 2008 - Present |
| Description: | • Design high speed NAND flash memory controller on Intel-Micron flash technology (IMFT). |
| Employer: | Sankara Eye Foundation |
| Position: | Active volunteer |
| Description: | A Bay-Area non-profit organization – organized and lead fundraising events, compeered shows, assisted in various event management tasks, write articles for the newsletter. |
| Employer: | Altera Corporation |
| Position: | Sr. Applications Engineer |
| Time period: | May 2008 - July 2008 |
| Description: | • Supported components, tools & IP focused on hardcopy (structured ASIC) & external memory interface technologies. Created technical documentation, performed lab testing, created example designs and worked closely with Altera's Engineering teams to improve the current and next generation external memory solutions. Supported the front-line support teams and helped resolve escalated issues. |
| Employer: | Advanced Micro Devices (AMD) Inc. |
| Position: | Design Engineer |
| Time period: | August 2003 - April 2008 |
| Description: | • Owned various logic implementation units towards successfully taping out multiple revisions of AMD’s Opteron microprocessor series that generated the mainstream revenue and established market leadership
• Worked on Execution unit, Load/Store Data Cache unit, Floating Point and North Bridge modules: Converted RTL to gate netlist, analyzed and optimized logic for timing closure, involved in all aspects of physical design - performed floor planning, place and route, fixed electrical issues, stitched repeaters, balanced scan chains, managed netlist regressions for functional verification and facilitated timely full chip sanity builds • Conceptualized, defined and managed the development of a new and efficient ECO flow that ensured predictability and better user control; convinced upper management and induced company-wide interest and adoption • Served as Timing Lead and Gate-simulation Verification Lead for Load/Store unit and Northbridge. • Represented and monitored the optimization team’s CAD needs in the CAD steering committee. As a CAD-Implementation coordinator, drove cad resources towards implementation methodology development. • Analyzed logic/power optimization results and recommended feature changes for new chip revisions. Provided quick turn around/feedback on mission critical fixes, that impacted AMD’s revenue and customer relations • Evaluated CAD tools & design flows; provided feedback; interacted with vendor s & helped with beta testing. Also developed infrastructure tools for one hot overlap analysis. • Worked on core-NB interface with multiple clock domains, owned the dual core interface module and addressed cross core issues, coordinated scan chain stitching, improved atpg coverage, re-architected integer multiplier • Worked closely with DFT, circuits, integration and verification groups on resolving scan chain issues, macro definitions, pin timing, LVS/DRC/integration issues. • Coordinated & interacted effectively with cross-site teams based in Sunnyvale, Austin, Boston, Fort-Collins, India Initiatives • Technology Seminar Coordinator: Organized Tech-talks inviting accomplished speakers within AMD and outside that enhanced cross team interactions and innovative discussions • Captain, University Campus Team for Purdue at AMD: Lead a team of 15 members – recruited members and host team meetings to plan & organize recruiting events on campus that establish & maintain relationship with Purdue University; write proposals to fund campus activities; promoted the “Wii gaming contest”, lecture series etc. • Initiated & drove a disk space recovery project, that reclaimed 60+TB of storage space & saved over a million dollars |
| Employer: | Cypress Semconductors |
| Position: | Design and Verification Engineer - Intern |
| Time period: | April 2003 - August 2003 |
| Description: | • As member of the Data Communication Division, designed and verified several RTL modules of the Generic Framing Procedure (GFP/TGFP) Framer/Deframer chip (LLD2F-16), generated directed and random test vectors for full-chip verification, acquainted with the various ITU standards, protocols and the interfaces such as SPI-3, GMII, RMII, RGMII, HSPI used in the chip and documented the findings. Used Verilog |
| Employer: | University of Wisconsin |
| Position: | Graduate Teaching Assistant |
| Time period: | August 2001 - May 2003 |
| Description: | • Conducted classes, set up examinations and home-works, graded tests, led discussions and maintained the course page for Electronic Circuits for four semesters
• Secured excellent student and professor evaluations over consecutive semesters and won the Teaching Excellence Award in 2003. Voted for as the ‘Best TA’ in Fall 2002 in the university |
EDUCATION
| University: | University of Wisconsin System - Madison |
| Time period: | 2003 |
| Degree: | Electrical & Computer Engineering, MSc |
| University: | University Of Madras |
| Time period: | 2001 |
| Degree: | Electronics and Instrumentation Engineering, BEng |
INFORMATION
| Hobbies: | • Indian classical (Carnatic) singer, perform occasionally at cultural events
• Involved with Bay Area community theater groups: NAATAK and KREA as a singer/actor in their plays. • Chess enthusiast: tournament player in high school/college. |
| Awards: | • Recipient of Gerald Holdridge Excellence in Teaching Award, University of Wisconsin – Madison, 2003
• Award for Academic Excellence, University of Madras; Ranked 9/1500 students. (Top - 0.5% of program), 2001 • Certified by the Central Board of Secondary Education for being among the top 0.1% of successful candidates of AISSCE, 1997 • Voted for as ‘The Best Teaching Assistant’ in the College of Engineering at UW- Madison in Fall 2002 • Presented papers & secured the first place in various nation level technical symposiums in India during undergraduate studies |
