perry brown
Experienced Electronic-Engineering Technician with over 15 years experience in developing manufacturing processes for new products, Studied Computer Electronics Tecnology from Mission College, Engineering Technicain-3 for 6 years at Intel Corporation
| Headline: | Entrepreneur |
| Skills: | Design, Engineering, Languages, Languages and Platforms, Product design, Software Engineering, System Administration, Unix, Windows, Windows applications |
| Interested in: | Consulting opportunities, Meeting new people, Patenting my idea, Professional opportunities, Receiving feedback |
| Schools: | University of California System - Santa Cruz |
WORK EXPERIENCE
| Employer: | Intel Corporation |
| Position: | Engineering Technician III |
| Time period: | January 2001 - December 2006 |
| Description: | •Mask Design custom layout of test structures working closely with engineering schematics and verbal instructions.
•Physical verification of layout using Hercules, especially DRC & LVS. •Generation and debug of test software for flash memory process. •Evolved formats for documenting layout to aid in wafer fabrication and yield analysis. |
| Employer: | Intel Corporation |
| Position: | Electronics Technician III |
| Time period: | January 1984 - December 2001 |
| Description: | •Learned CAD / EDA and physical verification tools to create test structures (H2 1995).
•Collected test data on non-standard fab (SRAM) material using automated testers |
| Employer: | Intel Corporation |
| Position: | Electronics Technician II |
| Time period: | January 1978 - December 1984 |
| Description: | •Collected test data on non-standard fab (SRAM) material using microscope and curve-tracer.
•basic tasks: •Run, debug and document problems in manual and automated test systems and software to sustain test of products (ex: SRAMs, microprocessors like Pentium, NOR Flash). •Analyze test data to support Device Physics Engineers in defining optimum processing of products. •Supported Engineering in special projects. •Trained junior R&D technicians in both layout and test systems. •Trained production operators in running test systems and new products. |
| Employer: | Intel Corporation |
| Position: | Engineering Operator |
| Time period: | January 1976 - December 1978 |
| Description: | •Learned Oxide Growth and oxide furnace profiling.
•Performed non-standard processing on SRAMs in the fab per written and verbal engineering instructions. |
| Employer: | Intel Corporation |
| Position: | Fab Operator |
| Time period: | December 1976 |
| Description: | •Mastered all ‘wet side’ photolithographic functions. |
EDUCATION
| University: | University of California System - Santa Cruz |
| Degree: | Psychology |
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