Jonathan Burrows
Applied Physics graduate from Caltech. Over 8.5 years of experience working with most of the world’s top semiconductor manufacturers on leading edge (down to 32 nm) FEOL and BEOL process characterization and yield improvement.
| Headline: | Engineer |
| Industries: | Cleantech, Nanotech |
| Skills: | Business, Electrical Engineering, Engineering, Industrial Engineering, Management |
| Location: | San Francisco, CA |
| Groups: | Berkeley-Stanford CleanTech Conference, Ignite Clean Energy (ICE) |
| Interested in: | Consulting opportunities, Employment opportunities, Finding team mates, Joining a startup, Meeting new people, Offering Expertise, Professional opportunities, Providing services to startups, Trading services |
| Schools: | California Institute of Technology |
WORK EXPERIENCE
| Employer: | PDF Solutions, Inc., San Jose, CA |
| Position: | Applications Manager |
| Time period: | May 2007 - March 2008 |
| Description: | PDF Solutions, Inc. is the leading provider of yield improvement consulting services and infrastructure for the integrated circuit (IC) manufacturing process lifecycle. The Company helps its customers, which include IDM’s, foundries, and fabless semiconductor companies, by addressing design and manufacturing interactions from product design to initial process ramps to mature manufacturing operations.
• Managed deployment and application of PDF infrastructure and methodologies needed to support use of PDF test chips on engagement projects. • Identified and continually collected key deployment and application metrics, and used metrics results to drive internal process development and improvements. • Worked with internal yield analysis software development group to spec new software features and bug fixes. • Supervised, trained, and career managed a team of applications engineers. • Worked with capital equipment vendors on joint development of inspection and failure analysis methodologies. • Developed and managed defect inspection and failure analysis BKM’s and application methodologies for use on all consulting projects. • Developed project cost models and resource plans for failure analysis and inspection applications on all projects. • Responsible for developing strategic partnerships with outside engineering analysis companies. |
| Employer: | PDF Solutions, Inc., San Jose, CA |
| Position: | Yield Consultant |
| Time period: | December 2006 - May 2007 |
| Description: | • Team member on three person consulting team working with major European IC manufacturer to identify and solve performance and yield problems for client’s CMOS image sensor process over multiple fabs.
• Responsibilities included working with client on identification and diagnosis of product/process yield loss mechanisms and creating a yield improvement plan for long-term manufacturing improvement as well as immediate yield issues that arose. • Continuous interaction with client at both engineering and management levels, including over 50% direct onsite client interaction and support. |
| Employer: | PDF Solutions, Inc., San Jose, CA |
| Position: | Project Manager |
| Time period: | August 2002 - December 2006 |
| Description: | • Managed test chip design projects for leading-edge semiconductor technology development.
• Supervised, trained, and career managed a team of test chip engineers. • Worked with sales and marketing groups to sell engagements and write engagement contracts and SOW’s. • Developed project cost models and resource plans for all design projects. • Scheduled and assigned design group resources (over 15 engineers). • Identified and continually collected key design through mask manufacturing process metrics, and used metrics results to drive internal process development and improvements. • Worked on product development, strategic roadmapping, standardization, benchmarking, and integration of several key products, resulting in multiple patent applications. • Worked with lithography simulation group on product analysis for lithography/OPC problem spot detection and printability test structure development. • Collaborated with legal consultants on technology IP protection. |
| Employer: | PDF Solutions, Inc., San Jose, CA |
| Position: | Test Chip Development and Application Engineer |
| Time period: | July 2000 - August 2002 |
| Description: | • Determined manufacturing process issues by working directly with clients, which included some of the world’s largest foundry, fables, and IDM semiconductor companies.
• Designed test chips to diagnose causes of process problems. • Supervised and trained other engineers. • Developed software specifications for various internal software tools used in design and verification process. • Worked on leading-edge semiconductor technology development. |
| Employer: | Intel Corporation, Santa Clara, CA |
| Position: | Process Engineer |
| Time period: | June 1999 - July 2000 |
| Description: | Intel is the world’s largest semiconductor company.
• Oversaw photolithography mask manufacturing and defect inspection for the two most critical IC layers. • Developed several tools and procedures to improve quality and cost efficiency of manufacturing process. • Qualified second source vendors of Intel technology. • Worked on leading-edge semiconductor technology development. • “Owned” production tool. • Supported production by addressing and troubleshooting problems encountered in the production line. |
| Employer: | FormFactor, Inc., Livermore, CA |
| Position: | Materials Research and Development Engineer (internship) |
| Time period: | May 1998 - August 1998 |
| Description: | FormFactor designs and manufactures advanced semiconductor wafer probe cards used by IC manufacturers.
• Developed new manufacturing methods to decrease production time of FormFactor’s products. |
| Employer: | California Institute of Technology, Pasadena, CA |
| Position: | Undergraduate Researcher (part-time during school and full-time over summers) |
| Time period: | May 1996 - May 1999 |
| Description: | • Developed and tested various unique materials for use in consumer, industrial, and military products. |
EDUCATION
| University: | California Institute of Technology |
| Degree: | Applied Physics, BSc |
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XunLight
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