Ilya Ivanchenko
| Headline: | Innocent Bystander |
| Skills: | C/C++, Engineering, Languages and Platforms, Software Engineering, SQL, System Administration, Unix, Web Development, Windows |
| Groups: | BASES, E-Challenge Competition 2008, E-Challenge Competition 2009, [INACTIVE] BASES E-Challenge 2010 |
| Interested in: | Helping friends, Meeting new people, Professional opportunities |
WORK EXPERIENCE
| Employer: | SyntheSys Research, Inc. (BERTScope) |
| Position: | Project Manager / Sr. Hardware Engineer |
| Time period: | January 2005 - April 2008 |
| Description: | Managed cross-functional design projects (mechanical, optical, system, board-level, FPGA, firmware) for new products. Contributed to the design of high-speed (12.5Gb/s) analyzers and test equipment for telecom and data transmission.
Lead the development of new fiber-optic test instruments on short schedule. Delivered test product for IEEE802.3aq 10GBASE-LRM, product introduced at OFC 2007. A derivative LTS product ships now. Developed optical clock recovery instrument DCRJ (link), now ships in volume. Delivered working 12.5Gb/s CRJ clock recovery prototype for OFC 2005 in 3 months. Developed digital part, FPGA and firmware. Managed ramp-up, pilot manufacturing and transfer to operations. CRJ product (link) is now shipping in volume under BERTScope and Tektronix (under OEM agreement, link) brand names with revenues of $1M/qtr. |
| Employer: | Pinnacle Systems, Inc. |
| Position: | ASIC Consultant |
| Time period: | November 2004 - January 2005 |
| Description: | Development and verification of ASICs for high-volume consumer products. Project management consulting, evaluation and analysis. |
| Employer: | Leapfrog Enterprises, Inc. |
| Position: | Sr. ASIC Engineer |
| Time period: | April 2002 - October 2004 |
| Description: | In charge of development and verification of ASICs for high-volume consumer products. Report to VP of Engineering. Taped out 4 SoC ASICs in 0.18um and 0.35um CMOS.
Lead a team of 4 and developed cost-saving high performance color STN LCD panel displays and controller IP. Enabled new flagship product (Leapster) and helped the product meet its cost target. Work also resulted in patent applications. Product got introduced with great success, received multiple awards and continues shipping today. Took ownership of a number of struggling ASIC projects and brought them to fast and successful tapeouts. Completed a number of concurrent ASIC projects, coordinated tasks in engineering and other groups (design, verification, backend, ECO, testing, manufacturing). ASIC design – models, RTL, verification, FPGA emulation, synthesis, DFT/scan/bist, place&route/ECO, ATE test vectors, bring-up and debugging, production ramp-up and yield improvement. |
| Employer: | Guzik Technical Enterprises |
| Position: | Project Manager, Sr. Software & FPGA Engineer |
| Time period: | January 1998 - December 2002 |
| Description: | In charge of development and verification of digital signal processing and measurement systems for disk storage instrumentation. Report to VP of Engineering.
Lead a team of 10 hardware, software and FPGA design engineers. Establish development, integration and verification methodology. System architecture, software/hardware partitioning, design and verify FPGA systems, develop C++ software. Hardware: Developed a number of FPGA-based designs, including company flagship real-time DSP with continuous throughput of 2GSample/s (16Gbit/s) supporting 1GHz real-time sampling speed. Developed advanced timing and jitter measurements and eye diagram analysis algorithms in FPGA. Software: Delivered commercial applications for Windows, including two for Tektronix digital oscilloscopes – “Jitter and Timing Analysis” and “Disk Drive Analysis”. Developed software and device drivers for company products. Developed co-simulation environment for parallel development and co-verification of hardware, software and VLSI/ASIC designs (Verilog-PLI). |
| Employer: | Institute Of Automation & Electrometry - Russian Academy of Sciences |
| Position: | R & D Engineer |
| Time period: | January 1992 - December 1998 |
| Description: | Department of network systems and multiprocessor computers.
Developed network systems hardware and C++ software, R&D, digital design, bus and network protocols, TCP/IP. Designed single-board VME computer compatible with Apple Macintosh. Working solo, performed system design, circuit design, PCB layout, firmware and device drivers design, PLD design and system bring-up. |
