Hrishikesh Sathawane
Electrical Engineering Manager with ten years experience within the semiconductor/hardware industry.
| Headline: | Engineer |
| Work status: | Employed Full-Time |
| Industries: | Cleantech, Nanotech |
| Skills: | Business, Electrical Engineering, Engineering, English, Languages, Leadership, Management, Marketing |
| Groups: | 2011 UC Berkeley Business Plan Competition, 2012 UC Berkeley Startup Competition, Berkeley-Stanford CleanTech Conference, UC Berkeley Business Plan Competition 2009-2010, [INACTIVE] UC Berkeley Business Plan Competition 2008-2009 |
| Interested in: | Brainstorming, Finding team mates, Growing my group, Meeting new people, Professional opportunities |
| Schools: | Indian Institute of Technology, Iowa State University, University of California System - Los Angeles |
WORK EXPERIENCE
| Employer: | Micron Technology Inc., San Jose, CA |
| Position: | Design Verification Manager |
| Time period: | January 2007 - Present |
| Description: | Manage verification teams in San Jose and Shanghai that run regressions using several thousand vectors on all the flash chip designs from Micron and Intel. Development of new OVM environment to generate coverage driven constrained random stimulus for full chip. Automate report generation for upper management. Interface with customers to make sure they have correct understanding of our chips.
• Co-ordinate projects across different sites such as San Jose, Boise, Japan, Italy and Shanghai. • Working with Technical Marketing team, manage a team that provides Technical support for models to all of Micron’s NAND Flash customers. • Drive adoption of new tools and more efficient methodologies to maximize the use of resources. • Improved Verification Coverage that reduced number of functional verification bugs found at back end by 10x. This resulted in fewer re-spins, saving over half million dollars per re-spin and faster time to market. • Improved Verification Time and created savings of over 50% , savings of at least $1 million per annum. • Added Scripts to automate flow and improved efficiency, timesavings of a few weeks per project. • Improved setup to make current test vectors portable to a newer interface saving work of 8 engineers over one month resulting in approx $80k in savings. • Interact with customers and work on memory models and their validation. This ensures that customers would face less problems during actual integration of their design with the real memory chips from Micron. |
| Employer: | Micron Technology Inc., San Jose, CA |
| Position: | Senior Design and Verification Engineer; Design Engineer |
| Time period: | January 2000 - December 2007 |
| Description: | Senior Design and Verification Engineer 2005 – 2007
Design Engineer 2000 – 2005 Design Digital and Analog blocks in NAND and NOR Flash Chips. Verify them using various digital and analog tools including Verilog, ESP-CV, hspice, nanosim, hsim. • Designed digital blocks like redundancy column latching circuit for memory array. • Designed analog blocks like tunable on-chip oscillator. • Standardize analog/digital easy-to-use verification environment for all the designers on our site. • STL (Simulation and Test Language) coding to generate pwl stimulus for HSPICE and Hsim easily. • Found a way to import tests directly from back-end (die testing) and run verilog simulations using them so issues can be found much earlier in the process saving company millions in re-spins. • Improved functional coverage by adding more directed tests and increasing vector coverage by 8x and made it easy to use this regression setup to verify different chips by different by engineers located at our international sites. • Found alternate solution for expensive ESP-CV tool resulting in savings of several $100,000/per annum. • Developed a user-friendly tool using html/php/javascript to gather verification data from files located on different servers in USA and other servers at company sites abroad. |
| Employer: | Micron Technology Inc. |
| Position: | Product Engineer |
| Time period: | January 1999 - December 2000 |
| Description: | Close Interaction and understanding of job functions of engineers involved in various stages of semiconductor manufacturing. From Designers to Probe, Test and Quality Assurance Engineers Debugging chips using simulations, packaged die with Board Level Testing, wafers using Micro-probing techniques, Probe flow. Helping Designers with LVS and other analog/digital simulations. |
EDUCATION
| University: | University of California System - Los Angeles |
| Time period: | 2008 - 2011 |
| Degree: | Sustainability, International, Marketing/Strategy, MBA |
| University: | Iowa State University |
| Time period: | 1997 - 1999 |
| Degree: | Electrical Engineering - Photovoltaic Solar Cells, MEng |
| University: | Indian Institute of Technology |
| Time period: | 1993 - 1997 |
| Degree: | Engineering Physics, BTech |
