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Elaine Ou

Master of the Universe

Headline: Innocent Bystander
Work status: Full-Time Student
Website: http://www.stanford.edu/~elaineo
Industries: Financial
Skills: Business, Electrical Engineering, Engineering, Investment, Software Engineering
Location: Stanford, CA
Groups: E-Challenge Competition 2009, [INACTIVE] BASES E-Challenge 2010
Schools: California Institute of Technology, Harvard University, Stanford University

FEATURED STARTUP

Truhedge

Truhedge Truhedge

Portfolio Protection Made Easy

  • Startup type: Competition Entry
  • Status: Active
  • Stage: Prototyping

WORK EXPERIENCE

Employer: Stanford University Integrated Circuits Group
Position: Graduate Research Fellow
Time period: August 2005 - Present
Description: • Studying circuit design for nonvolatile memory and 3-D applications.

Employer: Intel Corporation, Folsom, Calif.
Position: Design Engineer
Time period: May 2004 - July 2004
Description: • Designed error-correction hardware implementing a BCH code for multilevel Flash memory.

Employer: Harvard University VLSI Group
Position: Graduate Research Fellow
Time period: August 2003 - May 2005
Description: • Developed high-speed error correction circuits for semiconductor memory.

Employer: Situs Logic, Pasadena, Calif.
Position: Senior Design Engineer
Time period: May 2003 - May 2004
Description: • Developed CAD tools for asynchronous circuit design and layout.
• Designed the hardware for a test chip demonstrating asynchronous pulse logic.

Employer: Caltech Asynchronous VLSI Group
Position: Research Assistant
Time period: December 2001 - May 2003
Description: • Participated in design of asynchronous 80C51 microcontroller.
• Developed CAD tools to automate layout and optimization for asynchronous memory.

Employer: NASA Jet Propulsion Laboratory, Pasadena, Calif.
Position: Summer Undergraduate Research Fellow
Time period: May 2001 - August 2001
Description: • Developed network protocols for haptic devices in shared virtual environments.

Employer: Caltech Implementation of Computation Group
Position: Summer Undergraduate Research Fellow
Time period: May 2000 - August 2000
Description: • Worked on optimizing the architecture of field programmable gate arrays
• Developed a CAD tool for partitioning the placement of FPGAs

Employer: University of Southern California Micro Photonic Devices Group
Position: Summer Undergraduate Research Fellow
Time period: May 1999 - August 1999
Description: • Worked in the department of Electrophysics and Electrical Engineering fabricating
semiconductor lasers.

EDUCATION

University: Harvard University
Time period: 2002 - 2005
Degree: Computer Science, MSc

University: California Institute of Technology
Time period: 1998 - 2003
Degree: Electrical Engineering, BSc

University: Stanford University
Time period: 2004 - Present

PUBLICATIONS

Articles: Fast Error-Correcting Circuits for Fault-Tolerant Flash Memory.
Elaine Ou and Woodward Yang. Proc. of IEEE International Workshop on Memory
Technology, Design, and Testing. San Jose, Calif, August 2004
Energy-delay tradeoffs involving voltage scaling in synchronous and asynchronous systems.
Elaine Ou, Mika Nyström. Proc. of Fourth Asynchronous Circuit Design Working Group
Workshop. Turku, Finland, June 2004
An Eight-bit Digital Divider Implemented in Asynchronous Pulse Logic
Mika Nyström, Elaine Ou, Alain Martin. Proc. of Tenth IEEE Interational Symposium on
Asynchronous Circuits and Systems. Hersonissos, Crete, April 2004
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
Proc. of Ninth IEEE International Symposium on Asynchronous Circuits and Systems.
Vancouver, BC, May 2003
Optimization and Generation of Asynchronous Read-Only Memory
Elaine Ou, Mika Nyström, Alain Martin. Caltech CSTR, November 2002
Patents: Asynchronous Error-Correcting Circuits for High-Density Memory. Elaine Ou, Woodward Yang.

Elaine's Contacts (1)

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  • Ghyrn Loveness

    Working on silicon nanowire technology, EV infrastructure, and rural development startups