Bill Pontikakis
Computer Engineering graduate with MSc from Concordia University, currently pursuing PhD at École Polytechnique de Montreal.
| Headline: | Engineer |
| Website: | http://www.grm.polymtl.ca/~pontika |
| Skills: | Computer Engineering, Electrical Engineering, Engineering |
| Location: | Montreal, Quebec, Canada |
| Groups: | Ignite Clean Energy (ICE) |
| Interested in: | Consulting opportunities, Finding team mates, Meeting new people, Providing services to startups, Trading services |
| Tags: | circuit design, clock generation, computer and electrical engineering, energy efficient, frequency synthesis, integrated circuits, low power, semiconductors, systems on chip soc, vlsi |
| Schools: | Concordia University, Ecole Polytechnique |
WORK EXPERIENCE
| Employer: | CMOS Chip Fabrication |
| Position: | Work experience |
| Description: | • Custom IC Chip 1: Several ring oscillators were designed for subthreshold operation using bulk biasing techniques
• Custom IC Chip 2: Several ring oscillators and clock output buffer configurations were algorithmically designed for low-energy optimization. o Followed the analog custom IC design flow o Simulation in Cadence Virtuoso Simulator using HSPICE and SPECTRE o Layout using the Cadence Virtuoso Analog Layout. o Layout versus Schematic (LVS) using Assura o Design Check Rules (DRC) using Mentor Calibre o Tape out using TSMC 0.18 μm CMOS technology o Tested chip1 in a DIP 40-pin package using a high speed TEKTRONIX oscilloscope, a signal generator, multimeters, and power supplies. |
EDUCATION
| University: | Concordia University |
| Time period: | 2001 - 2003 |
| Degree: | Electrical Engineering, M.A.Sc. |
| University: | Concordia University |
| Time period: | 1996 - 2002 |
| Degree: | Computer Engineering, BEng |
| University: | Ecole Polytechnique |
| Time period: | 2003 - Present |
| Degree: | Electrical Engineering, PhD |
PUBLICATIONS
| Papers: | 1. An All-Digital Skew-Adaptive Clock Scheduling Algorithm for Multiprocessor Systems on Chips (MPSoCs) Syed Rafay Hasan, Bill Pontikakis, Yvon Savaria; 2009 IEEE International Symposium on Circuits and Systems (ISCAS 2009), Lecture Acceptance Rate 45%
2. A Novel Phase-Locked Loop (PLL) Architecture Without an Analog Loop Filter for Better Integration in Ultra-Deep Submicron SoCs Bill Pontikakis, Hung Tien Bui, Fran?is-Raymond Boyer, Yvon Savaria; 2008 Joint IEEE NEWCAS-TAISA Conference (NEWCAS-TAISA 2008 ), Lecture 3. Precise Free-Running Period Synthesizer (FRPS) with Process and Temperature Compensation Bill Pontikakis, Hung Tien Bui, François-Raymond Boyer, Yvon Savaria; 2007 Joint IEEE MidWest Symposium on Circuits And Systems (MWSCAS 2007) and IEEE NorthEast Workshop on Circuits And Systems (NEWCAS 2007) , Lecture 4. A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs Bill Pontikakis, Hung Tien Bui, François-Raymond Boyer, Yvon Savaria; 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), Lecture Acceptance Rate 49% 5. A 0.8V Algorithmically Defined Buffer and Ring Oscillator Low-Energy Design for Nanometer SoCs B. Pontikakis, F.-R. Boyer, Y.Savaria; 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), Poster Acceptance Rate 59% 6. Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period B. Pontikakis, F.-R. Boyer, Y.Savaria; 5th IEEE International Workshop on System on Chip for Realtime Applications (IWSOC 2005) 7. A Variable Period Clock Synthesis (VPCS) Architecture for Next-Generation Power-Aware SoC Applications F.-R. Boyer, H. G. Epassa, B. Pontikakis, Y.Savaria, W. Ling; 2nd IEEE Northeast Workshop on Circuits and Systems, 2004. (NEWCAS 2004), Lecture Acceptance Rate 71% Cited by 5 (According to scholar.google.com as of February 2009) 8. A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications B. Pontikakis, M. Nekili; IEEE International Symposium on Circuits and Systems, 2002. (ISCAS 2002), Lecture 9. A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications B. Pontikakis, M. Nekili; Proceeding of the 13th IEEE International Conference on Microelectronics, 2001. (ICM 2001) |
INFORMATION
| Memberships: | • Member of the Institute of Electrical and Electronic Engineers (IEEE)
• IEEE Solid State Circuits Society • IEEE Computer Society • IEEE Circuits and Systems Society • Member of the Public Relations Committee at Cretan Association of Montreal ( 2008-present) The committee is acting as the planning and organizing committee for cultural events hosted by the Cretan Association of Montreal. • Member of the Academic Tribunal Hearing Panel, Concordia University ( 2003-2005 ) Made decisions for hearings, both first-level as well as appeal provided for in the Code of Rights and Responsibilities, the Code of Conduct (Academic), the Academic Re-evaluation Procedures, and the Graduate Academic Hearing Procedures. • Program for Leadership and University Success (PLUS) Certificate, Concordia University An 18-hour program that introduces the basic skills, tools, and knowledge needed to become an effective leader. |
| Awards: | • Ph.D. University bursary of $18,000 per year, École Polytechnique de Montreal
• M.A.Sc. Engineering Faculty Research Award of $5,000, Concordia University • ReSMiQ undergraduate microelectronics research award of $3,000 (Only three awarded) |
