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Arun Kumar

Indian, 24, majoring in Electrical Engg. at Stanford. Interested in biz. consulting, Computer Graphics.

Headline: Engineer
Work status: Full-Time Student
Industries: Entertainment, Financial, Media
Skills: Architecture, Business, Computer Engineering, Design, Electrical Engineering, Engineering, English, Entrepreneurship, Languages, Languages and Platforms, Leadership, Perl, Product design, Public Relations, Software Engineering, System Administration, Unix, Windows, Writing
Next step: When I graduate I want to have a startup of my own, tackling the prevalent socio-economic challenges, shaping and improving the lives of millions of people in the third world countries.
Location: Stanford University
Groups: E-Challenge Competition 2008, E-Challenge Competition 2009, [INACTIVE] BASES E-Challenge 2010
Interested in: Brainstorming, Consulting opportunities, Creating a group, Employment opportunities, Finding team mates, Giving back, Growing my group, Helping friends, Internships, Investing in projects, Joining a startup, Meeting new people, Participating in a competition, Patenting my idea, Professional opportunities, Providing services to startups, Supporting my investments, Trading services
Tags: computer graphics, piezocharge, rfid consulting, vlsi circuit design
Schools: Stanford University

WORK EXPERIENCE

Employer: Baker Hughes Singapore (Pvt.) Ltd
Position: R&M Manager
Time period: March 2007 - August 2007
Description: Managed development, training and personnel planning of all R&M Tech. Responsible to provide a
safe working environment by minimising hazards in the work place. Worked towards maintaining the
R&M cost centre budget within planned levels, reducing product downtime and improving maintenance
efficiency across all product lines.

Employer: Texas Instruments
Position: Design Engineer
Time period: June 2005 - March 2007
Description: Mostly involved in VLSI circuit design. Was a member of the RFID business development group.

Employer: Texas Instruments
Position: Summer Internship
Time period: May 2004 - July 2004
Description: “Delay Fault Testing of VLSI Circuits”
Advisor: Jais Abraham
Carried out several research works related to delay fault testing such as fault classification, Automatic
Test Pattern Generation (ATPG) and scan compression techniques.

EDUCATION

University: Stanford University
Time period: 2007 - 2009
Degree: Electrical Engg., MEng

PUBLICATIONS

Articles: [1] J. Abraham, A. Kumar and U. Goel, “Multi-cycle Sensitizable Transition Delay Faults”, IEEE VLSI Test
Symposium, 24th IEEE Volume, pp. 6-, April 2006.
[2] A. Kumar and A. Datta, “Built-in Self Repair of Embedded Memories in a SOC”, Texas Instruments
Symposium on Test, Dallas, August 2006.
[3] A. Kumar and A. Jain, “Implementation of CORDIC Algorithm on FPGA”, Techkriti, Annual Technical
Festival, Indian Institute of Technology, Kanpur
Papers: "Multi-cycle sensitizable path delay faults", IEEE VTS'2006

INFORMATION

Sports: Cricket, Badminton
Hobbies: Music, Movies
Awards: Baker Hughes Leadership Excellence and Development Program (LEAD) May 2007
Top Graduate Award
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems August 2006
Reviewer
Texas Instruments, India Technical Conference (TIITC) October 2005
Best Poster Award
Annual Tech. Festival Cognizance, Indian Institute of Technology, Roorkee February 2004
First Prize, long term Modeling and Simulation contest (MATLAB Platform)
National Council of Education Research and Training (NCERT)
,
INDIA March 2000
National Talent Award, 1998 - 99
Homi Bhabha Centre for Science Education, Tata Inst. of Fundamental Research February 2001
Top 1% in Indian National Chemistry Olympiad, 2000-01
Top 1% in Indian National Physics Olympiad, 2000-01
Other Awards
Top 0.1% in Chemistry at All India Senior Secondary Certificate Examination, 2000-01 May 2001
Top 0.1% in Mathematics at All India Senior Secondary Examination, 1998-99 May 1999

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